signal processing technologies, inc. 4755 forge road, colorado springs, colorado 80907, usa phone: (719) 528-2300 fax: (719) 528-2370 website: http://www.spt.com e-mail: sales@spt.com spt5510 16-bit, 200 mwps ecl d/a converter applications ? high-precision arbitrary waveform generation ? test and measurement instrumentation ? digital waveform synthesis ? microwave and satellite modems ? disk drive test equipment ? industrial process control ? military applications block diagram general description the spt5510 is a 16-bit, 200 mwps digital-to-analog converter designed for high-resolution waveform synthesis for test and measurement instrumentation applications. it features true 16-bit linearity, with differential non-linearity of typically 0.6 lsb and integral non-linearity of 0.75 lsb. it features ? 16-bit, 200 mwps digital-to-analog converter ? differential linearity of 0.6 lsb (typical) ? integral linearity of 0.75 lsb (typical) ? fast settling time: 35 ns to 0.0008%; 25 ns to 0.01% ? low glitch energy ? on-chip voltage reference ? ecl compatibility has a very high-speed update rate of up to 200 mhz and is ecl compatible. it has an ultrafast settling time of 25 ns to 0.01% and 35 ns to 0.0008%. the spt5510 operates over an industrial temperature range of C40 c to +85 c and is available in a 10 x 10 mm, 44-lead metric quad flat pack (mqfp) plastic package. 16 16 12 12 16 i out i out clk digital inputs d15Cd0 bandgap reference bg out r set amp inb + C ref amp amp out amp cc 20 10 bias reference cell bias current cells d15Cd12 d11Cd0 msb latch lsb latch input latch msb decoder lsb buffer i out i out ref in
spt 2 9/27/00 spt5510 dc performance 1 resolution 16 bits differential linearity vi C1.95 0.6 1.95 lsb differential linearity t min Ct max iv C4.0 1.0 4.0 lsb integral linearity vi C1.95 0.75 1.95 lsb integral linearity t min Ct max iv C4.0 1.5 4.0 lsb integral linearity drift iv C0.2 0.2 lsb/ c offset drift t min Ct max iv C2.5 2.5 ppm fs/ c monotonicity v 15 bits output capacitance v 10 pf gain error i C2 0.4 2 % fs gain error tempco with ext reference v 50 ppm fs/ c gain error tempco with internal bandgap ref v 50 ppm fs/ c offset error i C4 4 m a compliance voltage iv C1.2 2 v output resistance iv 0.88 1.1 1.32 k w dynamic performance conversion rate iv 200 mhz settling time t st 2 settling to 0.01% v 25 ns settling to 0.0008% v 35 ns delay time t d v2ns glitch energy v 30 pv-s full scale output current with on-chip references v 19 ma rise time/fall time r l = 50 w v2ns spurious free dynamic range ? out =5 mhz; ? clock =30 mhz 10 mhz span v 84 db ? out =10 mhz; ? clock =100 mhz 10 mhz span v 76 db absolute maximum ratings (beyond which damage may occur) 1 supply voltages negative supply voltage (v ee ) ................................. C7 v a/d ground voltage differential ................................ 0.5 v input voltages digital input voltage (d15Cd0, clock)... ........... C2.5 to 0 v ref amp input voltage range .......................... C2.5 to 0 v reference input voltage range (ref in) ...... v ee to C2.5 v output currents bandgap reference output current ..................... 500 m a ref amplifier output current ................................ 2.5 ma temperature operating temperature ............................... C40 to +85 c junction temperature .......................................... +150 c lead, soldering (10 seconds) ............................. +250 c storage .................................................... C65 to +150 c electrical specifications t a = 25 c, v ee =C5.2 v 5%, 50% duty cycle clock, unless otherwise specified. test test spt5510 parameters conditions level min typ max units note : 1. operation at any absolute maximum rating is not implied. see electrical specifications for nominal operating conditions. 1 measured at 0 v output using i-v. 2 measured as voltage settling for mid-scale transition; r l = 50 w .
spt 3 9/27/00 spt5510 electrical specifications t a = 25 c, v ee =C5.2 v 5%, 50% duty cycle clock, unless otherwise specified. test test spt5510 parameters conditions level min typ max units power supply requirements negative supply current (C5.2 v) t min Ct max vi 115 150 ma nominal power dissipation v 600 800 mw power supply rejection ratio d v supply = 5 % i C0.6 0.002 0.6 % fs voltage input and control bandgap reference voltage v C1.2 v bandgap output current t a =25 c 10 c iv C110 16 220 m a ref amp bandwidth 3 v 40 mhz ref amp input current v 16 m a ref amp output current v 200 m a ref in operating voltage v C3.4 v digital inputs logic 1 voltage t min Ct max vi C1.0 C0.8 v logic 0 voltage t min Ct max vi C1.7 C1.5 v logic 1 current C0.8 v v 2.5 m a logic 0 current C1.8 v v 0 m a input capacitance v 3 pf input setup time (t s ) iv 3.0 ns input hold time (t h ) iv 0.5 ns clock pulse width (t pwh ) iv 1.5 ns 3 ref amp bandwidth is limited by its compensation network test level codes all electrical characteristics are subject to the following conditions: all parameters having min/max specifi- cations are guaranteed. the test level column indicates the specific device testing actually performed during pro- duction and quality assurance inspec- tion. any blank section in the data column indicates that the specification is not tested at the specified condition. test level test procedure i 100% production tested at the specified temperature. ii 100% production tested at t a = +25 c, and sample tested at the specified temperatures. iii qa sample tested only at the specified temperatures. iv parameter is guaranteed (but not tested) by design and characterization data. v parameter is a typical value for information purposes only. vi 100% production tested at t a = +25 c. parameter is guaranteed over specified temperature range.
spt 4 9/27/00 spt5510 theory of operation the spt5510 is a segmented 16-bit current-output dac. the four msbs, d15Cd12, are decoded to fifteen unit cells (current sinks). the remaining bits (d11Cd0) are binary; bits d9Cd0 are derived from an r-2r ladder. all cells are laser trimmed for maximum accuracy. the block diagram shows the basic architecture. all output cells are always on, with the data determining whether a given cells current is routed from i out or i out . this provides nearly constant power dissipation indepen- dent of data and clock rate. it also reduces noise transients on power and ground lines. the reference loop utilizes an msb-weighted cell and pro- vides a gain of about 16 to the output. the on-chip refer- ence amplifier has very high open-loop gain and is offset trimmed to provide a very low temperature drift (typically <10 ppm/ c gain drift). power supply and grounding the spt5510 requires a single C5.2v power supply. all supply pins attach to a common on-chip power bus and should be treated as analog supplies. for best settling per- formance, each supply pin should be decoupled as shown in figure 1 C typical interface circuit. there are three separate on-chip ground busses. dgnd pins should be tied together and connected to system ground through a ferrite bead. refgnd and ognd pins should be tied directly to the spt5510s ground plane and connected to system ground through a ferrite bead. it is critical that refgnd and ognd are very tightly coupled, as any differential signal (dc offset, noise, etc.) will be transmitted to the output. two of the ognd pins can be disconnected from the ground plane and used as sense lines for a current-to-voltage converter, as shown in the outputs section. dgnd dgnd dgnd dgnd ognd ognd ognd ognd av ee av ee av ee av ee av ee av ee av ee av ee c1 c2 c3 c4 c5 .01 m f .01 m f .01 m f .01 m f .01 m f r1 r2 r3 r4 r5 r6 10 10 10 10 10 10 c17 c16 c15 c14 2.2 m f 2.2 m f 2.2 m f 2.2 m f 10 44 24 33 40 42 35 37 39 43 11 13 14 23 34 38 1 2 3 4 5 6 7 8 25 26 27 28 29 30 31 32 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c6 .01 m f c11 47 pf c10 47 pf c9 47 pf c8 .01 m f c7 .01 m f c12 10 pf c13 20 pf 50 r9 50 r8 1k r7 1k refgnd refgnd clk bg out amp inb r set amp cc amp b amp out ref in i out i out 9 22 12 16 18 17 19 15 20 21 41 36 c1Cc13 surface mount ceramic chip c14Cc17 tantalum r1Cr6 carbon film 1/4 w r7Cr10 surface mount ceramic chip fb ferrite bead is to be located as closely to the device as possible. spt5510 av ee r10 fb av ee input data output complementary output figure 1 C typical interface circuit
spt 5 9/27/00 spt5510 wideband decoupling is required for optimum settling per- formance. this may require several capacitors in parallel, and series resistors when appropriate, to reduce resonance effects. some applications may need only a single capaci- tor; however, decoupling influences both long- and short- term settling, so caution is urged. your application may require some research to determine the optimum power supply decoupling network. digital inputs and timing each digital input is buffered, decoded, and then latched into d flip-flops which drive the output switches. master- slave flip-flops are not used; thus, there is only a 1/2 clock period delay (max) from data change to output change. in this architecture, clock and data edge speeds (i.e., rise/fall times) may affect data feedthrough. using a data edge of approximately 0.8 ns will cause data feedthrough of about 10 pv-s, while a 5 ns data edge will reduce the feedthrough to about 4 pv-s. data lines may include series resistors or rc filters for edge control if desired. the clock signal controls when the data is latched into the flip-flops. when the clk is high, the dac is in track mode. a negative going clk latches the data. if clk is held low, the dac is in hold mode. see figure 2. outputs the output is comprised of current sinks, r-2r ladder, and associated parasitics. see figure 3 for an equivalent output circuit. the dacs full-scale output current when using the internal reference amplifier is determined by the voltage at pin amp inb and the r set resistance. it can be found (to within an lsb) by using the following formula: i out fs = (amp inb /r set ) x 16 the inputs determine whether the current from each sink comes from i out or i out as follows: code (d15 is msb) i out i out 0 (zero scale) no current all current 32768 (mid-scale) i out = i out i out = i out 65535 (full-scale) all current no current differential outputs facilitate maximum noise rejection and signal swing. the dac is trimmed using a current to voltage (i-v) converter which provides a virtual ground at the out- puts and includes sense lines to mitigate the impact of bus drops. operating into a load other than a virtual ground will introduce a slight bow at the output. this bow is related to the current sinks finite output impedance and ladder impedance. an example circuit using an i-v converter is shown in figure 4. note that resistor and op-amp self heating over the dacs full-scale range will introduce additional temperature depen- dence. the op-amp and feedback resistor must both have very low tempcos if the dacs intrinsic gain drift is to be maintained. a sense line helps reduce wire effects C both ir loss and temperature drift. figure 2 C timing diagram clk data i out t d t h t st i out t s t h = hold time t d = time to output valid t s = setup time t st = settling time figure 3 C equivalent output circuit 10 pf 1.1k av ee i out or i out + C + C ognd ognd ognd ognd gnd gnd 250 250 bnc "i out i out bnc "i out " i out figure 4 C i-v converter
spt 6 9/27/00 spt5510 the feedback resistor should be matched to r set to reduce gain drift. also, the op amps ground reference should be the same as r set s to reduce gain and offset errors. a com- posite amplifier may be required to obtain optimal dc perfor- mance. a differential circuit may be used; a common heat sink covering both sides (op amps and resistors) will help reduce temperature effects. achieving good settling performance requires careful board layout with multiple decoupling circuits and very clean power and ground routing. it is important that digital switch- ing currents do not flow across analog input (ref in ) and output signals. terminations must be broadband and near the device. measuring settling performance is quite chal- lenging and requires several test systems to ensure settling errors from the instruments are not included. dynamic performance characteristics (e.g., settling, rise and fall times, etc.) were measured with the outputs termi- nated to ground through 50 w resistors. sfdr was deter- mined using a transformer to convert the output from differ- ential to single-ended as shown in figure 5. the spt5510 is designed primarily for step and settle or narrowband rf applications. the second harmonic generally dominates wideband sfdr measurements, although close-in spurs are very small. bandgap voltage reference the on-chip bandgap voltage reference is designed to bias the non-inverting input of the reference amplifier (amp inb ) through a resistor equal to r set to help compensate the ref- erence amplifier (see the following section). if the bandgap voltage is required by another dac, or elsewhere in the sys- tem, it must be buffered with a precision op amp configured as a high impedance (e.g., unity gain follower) buffer. a resistor, or rc filter, plus a ferrite bead will help isolate the output from the reference amplifiers compensation and high-frequency charge pulses produced during operation. the output should always be very carefully checked for oscillations using a sensitive, wideband oscilloscope and spectrum analyzer. reference amplifier the reference amplifier is a highly temperature-stable driver to bias the precision current sinks. the reference amplifier should only be used to drive ref in . additional loads will change the amplifiers compensation, which can lead to instability and other settling issues. there are two reference amplifier outputs: amp out and amp cc . amp out has a 20 ohm series resistor between the output of the reference amplifier and the amp out pin; amp cc has a 10 ohm resistor. these parallel outputs aide compensation and decoupling. the open-loop output impedance is approximately 1200 ohms. reference amplifier compensation is key to achieving high performance. without proper compensation, oscillations that affect accuracy and settling time will occur. figure 6 shows a typical reference amplifier compensation circuit. note that several small value capacitors are used from ref in to ground. this is to provide suitably low impedance i out 25 25 i out figure 5 C transformer output circuit figure 6 C reference amplifier circuit + C 20 w 10 w 19 20 amp cc amp out 50 w 15 v ee 20 pf 1 k w 1 k w r set bg out 0.01 m f ref amp c1 c2 c3 47 pf each spt5510 dac 16 18 17 21 10 pf 0.01 m f all components are ceramic chip-type. amp b ref in
spt 7 9/27/00 spt5510 long-term stability versus temperature as with all high-speed, high-resolution digital-to-analog con- verters, the initial accuracy of the device will degrade with both time and temperature. the graph shown in figure 7 can be used to determine the expected change in linearity per- formance over time when the device is operated at various ambient temperatures. this graph shows how long it will take for the spt5510 linearity to change by 8 ppm (or 1/2 lsb) at any operating temperature. the top curve shown represents integral nonlinearity (ile) changes; the bottom curve shows differential nonlinearity (dle) changes. figure 7 C linearity performance over time temperature ( c) expected time required to produce an 8 ppm (1/2 lsb) linearity (ile or dle) shift as a function of temperature. 0 20 40 60 80 100 120 10 2 10 3 10 4 10 5 10 6 10 7 1 month 1 year 100 years 1000 years (hours) ile dle around 300 mhz, the amplifiers phase crossover point. the unity-gain bandwidth is roughly 700 mhz. larger value capacitors exhibit lower self-resonance frequency and thus may not adequately compensate the reference amplifier. large capacitors may also introduce low frequency tails which increase settling time. the dac itself exhibits very broadband switching spikes (charge kickback) at the r set node, which can contribute to amplifier instability if not sup- pressed. note that the amp inb input must not be directly bypassed, as this will short all feedback to ground, leading to severe oscillation. compensation must be optimized for each application. as with any high-speed, high-resolution design, attention must be paid to grounding, decoupling, and parasitic elements that may cause instability. it may be wise to use a guard ring, and/or clear the board ground, around the reference amplifiers inputs. all traces must be short, and capacitors with high self-resonance must be used. compensation is perhaps the most challenging aspect of setting up the spt5510. by slowly switching a full-scale data input (generating a low-frequency square wave), with appropriate clock timing, the dacs output can be observed using a suitable oscilloscope and spectrum analyzer to observe and suppress any oscillations caused by board and decoupling parasitics. consult spt applications for further assistance if required. package outline 44-lead mqfp index a b c d pin 1 e f g h i j k inches millimeters symbol min max min max a 0.5098 0.5295 12.95 13.45 b 0.3917 0.3957 9.95 10.05 c 0.3917 0.3957 9.95 10.05 d 0.5098 0.5295 12.95 13.45 e 0.0311 0.0319 0.79 0.81 f 0.0118 0.0177 0.30 0.45 g 0.0768 0.0827 1.95 2.10 h 0.0039 0.0098 0.10 0.25 i 0.0287 0.0406 0.73 1.03 j 0.0630 ref 1.60 ref k0 7 0 7
spt 8 9/27/00 spt5510 pin functions name function d15Cd0 digital input bits C all inputs high sends all current to i out , none to i out clk clock C latches d flip-flops i out analog current output i out complementary analog current output bg out bandgap voltage reference amp inb ref amps inverting input r set ref amps non-inverting input C connection for reference-current-setting resistor, nominally 1k w to ground amp out bias voltage for output current switches C drives ref in (on-chip 20 w resistor for compensation) ref in bias voltage node for output current switches C driven by amp out amp b used to decouple ref amps circuits to av ee amp cc amp out plus on-chip 10 w series resistor for compensation av ee negative supply C C5.2 v dgnd digital ground return ognd output ground return refgnd reference amplifier ground return ordering information part number temperature range package SPT5510SIM C40 to +85 c 44l mqfp signal processing technologies, inc. reserves the right to change products and specifications without notice. permission is her eby expressly granted to copy this literature for informational purposes only. copying this material for any other use is strictly prohibited . warning C life support applications policy C spt products should not be used within life support systems without the specific written consent of spt. a life support system is a product or system intended to support or sustain life which, if it fails, ca n be reasonably expected to result in significant personal injury or death. signal processing technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. it is therefore not recommended, and exposure of a device to such a process will void the product warranty. pin assignments dgnd av ee ognd ognd av ee av ee ognd i out ognd av ee refgnd av ee av ee amp b bg out r set amp inb amp cc amp out ref in refgnd dgnd d0 (lsb) d1 d2 d3 d4 d5 d6 d7 dgnd av ee (msb) d15 d14 d13 d12 d11 d10 d9 d8 clk dgnd av ee 11 10 9 8 7 6 5 4 3 2 1 23 24 25 26 27 28 29 30 31 32 33 22 21 20 19 18 17 16 15 14 13 12 34 35 36 37 38 39 40 41 42 43 44 spt5510 44-pin mqfp i out
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